In many integrated circuit designs it can be desirable to provide a reference circuit. A reference circuit can provide a current and/or voltage at a generally known value. Reference circuits can have numerous applications, including but not limited to establishing a reference voltage to detect input signal levels, establishing a lower supply voltage to some section of a larger integrated circuit (e.g., memory cell array), establishing a reference voltage/current to determine the logic value stored in a memory cell, or establishing a threshold voltage for some other functions.
Reference circuits can be non-biased or self-biased. Non-biased reference circuits can rely on discrete voltage drop devices to arrive at a reference level. For example, a non-biased reference circuit can include resistor-diode (or diode connected transistor) arranged in series between a high supply voltage and a low supply voltage. A drawback to such approaches can be that a current drawn can be proportional to supply voltage. Thus, a higher supply voltage can result in a higher device current (ICC). This can be undesirable for low power applications.
Self-biased reference circuits can rely on transistor biasing to provide a reference current that is less variable (or essentially not variable) in response to changes in power supply voltage. Self-biased reference circuits almost always operate in conjunction with a start-up circuit. A start-up circuit can help establish potentials at particular nodes in a power-up (or similar operation) in order to ensure that the reference circuit is operating properly.
To better understand various features of the present invention, a conventional self-biased reference circuit with corresponding start-up circuitry will now be described.
FIG. 5 shows a first conventional self-biased referenced circuit 500 and corresponding start-up circuit 502. Self-biased referenced circuit 500 can be a “beta-multiplier” reference circuit that includes a first current mirror formed by p-channel metal-oxide-semiconductor (PMOS) transistors P51 and P52, a second current mirror formed by n-channel MOS (NMOS) transistors N51 and N52, and a resistor R51. Transistor N52 can be scaled in size with respect to transistor N51. For example, transistors N51 and N52 can have the same channel lengths, but a width of transistor N52 may be “K” times that of N51, where K is greater than one. In this way, a beta multiplication can occur.
Self-biased reference circuit 500 can include a bias node 504 formed at the drain-drain connection between transistors P51 and N51. When a bias node 504 reaches a predetermined potential, a self-biased reference circuit 500 can reach a stable operating point and provide a reference voltage/current for use in a larger integrated circuit.
A start-up circuit 502 can place bias node 504 at a stable operating point in a start-up operation. A start-up circuit 502 can include a PMOS current supply transistor P53, a PMOS pull-up transistor P54, a current mirror formed by NMOS transistors N53 and N54, and a resistor R52.
The circuit of FIG. 5 operates as follows. The circuit can be placed in an off condition by placing a bias node (biasp) of current mirror P51/P52 to a high supply voltage Vcch, and placing a bias node (biasn) of current mirror N51/N52 to a low supply voltage Vgnd. In such an arrangement, current through transistor P53 can be essentially zero.
In a start-up operation, a node (“Start” at the gate of transistor P54) can discharge toward a low supply voltage Vgnd through transistor N54. This can turn on transistor P54, which can then charge node biasn towards high supply voltage Vcch. Once node biasn reaches Vtn (the threshold voltage of transistors N51/N52), node biasp can begin discharging toward the low power supply voltage Vgnd. Once nodes biasp & biasn reach stable values, current supplied by transistor P53 can begin dominating that drawn by transistor N54, and node Start can be pulled to a high power supply voltage Vcch, thereby turning off transistor P54 and ending the start-up operation.
The circuit of FIG. 5 can be conceptualized as comparing a current drawn by self-biased reference circuit Ibeta (i.e., a beta multiplier current) with reference current Iref (that drawn by transistor N53). If a beta multiplier current is less than the reference current (through transistor N54), it can turn on the start-up circuit. In such an arrangement, a beta multiplier current Ibeta can be independent of the level of a power supply voltage Vcch. However, reference current Iref remains dependent on the level of power supply voltage Vcch.
A drawback to a conventional circuit like that shown in FIG. 5 can be lack of flexibility and large circuit components needed for implementation. In particular, if the circuit of FIG. 5 is optimized for use at higher external voltage levels and fast transistor speeds (fast “corners”), at lower voltages and lower transistor speeds (due to manufacturing variations, for example), the conventional circuit can fail to meet a minimum needed start-up time. Further, to arrive at a small reference current Iref, relatively large resistor R52 is needed. For example, achieving a 30 nA reference current at a supply voltage Vcch of 6.0 V can require 200M ohms of resistance. Such a large resistance can consume undesirably large amounts of area in an integrated circuit.
Two other conventional self-biased reference circuits are shown in FIGS. 6A and 6B. These circuits can include some of the same circuit components as that of circuit 500 in FIG. 5. Accordingly, like components are referred to by the same general reference characters.
The circuit 600 of FIG. 6A differs from the circuit of 500 in that an NMOS start-up transistor N65 can be included that is “diode” connected between the nodes biasp and biasn. The circuit 650 of FIG. 6B differs from the circuit of 500 in that two NMOS start-up transistors N66 and N67 can be connected in series between nodes biasp and biasn. The circuit of FIG. 6B is aimed at higher power supply voltages than that of FIG. 6A. In both arrangements, the circuit can be initially off by driving node biasp to a high supply voltage Vcch and node biasn to a low supply voltage Vgnd.
In a start-up operation, the start-up transistor(s) (N65 or N66/N67) can discharge node biasp toward node biasn. Once the nodes reach a stable level the path created by the start-up transistor(s) can be disabled, and the circuit can operate in a self-biased fashion.
A drawback to the circuits of FIGS. 6A and 6B can also be lack of flexibility. In the case of circuit 600, if Vcch>2*Vtn+Vtp, transistor N65 can start leaking. This can undesirably change the potentials nodes biasp and/or biasn, thus introducing instability into the generated reference current/voltage. It is understood that Vtn is a threshold voltage for NMOS transistors of the circuit while Vtp is a threshold voltage for PMOS transistors of the circuit.
In the case of circuit 650 shown in FIG. 6B, if Vcch<3*Vtn+Vtp, transistors N66/N67 can fail to start-up the circuit (i.e., establish stable bias voltages at nodes biasp and biasn).
Accordingly, if a circuit 650 is optimized for a higher power supply voltage, such a circuit may fail to start-up properly at a lower voltage. At the same time, if a circuit 600 is optimized for low voltages, it may become unstable at high voltages.
It would be desirable to arrive at a self-biased reference circuit that can operate at a wider range of power supply voltages without the drawback of the above conventional approaches.
It would also be desirable to arrive at a self-biased reference circuit that can operate at low current levels and yet not require large resistors.